This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-086381, filed Mar. 27, 2000, the entire contents of which are incorporated herein by reference.
This invention relates to a differential amplifier which is fundamental in processing an analog signal in a MOS integrated circuit and to a filter circuit using the differential amplifier as a transconductance circuit.
To process an analog signal with high quality, it is necessary to cause the circuit to operate linearly. In general, however, it is difficult to realize an analog circuit with good linearity using a CMOS circuit. The reason for this is that the approach of expanding the linear range using resistances is not effective, because the MOS transistor has a lower gm (transconductance) than that of the bipolar transistor, and that the MOS transistor itself has a square-law characteristic in the normal operating region. Thus, the approach of realizing an amplifier with a wide linearity by taking advantage of the square-law characteristic of the MOS transistor has been proposed.
A basic one of this approach has been proposed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 10-65461. The principle of the approach is shown in FIG. 1. The circuit of FIG. 1 is composed of a pair of MOS transistors M1, M2 whose sources are grounded. Consider a case where a complete differential signal is inputted to the circuit. It is assumed that both of the transistors M1 and M2 are operating in the saturation region (pinch-off region). To simplify the explanation, the short channel effect is not taken into consideration. At this time, using the values of the main parameters, k and Vth, the characteristic of each of the MOS transistors M1, M2 can be expressed as:
I=(k/2)(VGSxe2x88x92Vth)2xe2x80x83xe2x80x83(1) 
where I is the drain current, VGS is the gate-source voltage, Vth is the threshold voltage inherent to the transistor, and k is the constant xcexcCOXW/L where W is the gate width, L is the gate length, COX is the gate capacity, and xcexc is the carrier mobility of the channel.
Using equation (1), the descriptive equations for the operation of the transistors M1 and M2 can be expressed as follows:
M1: Iout+=(k/2)(VGS1xe2x88x92Vth)2xe2x80x83xe2x80x83(2) 
M2: Ioutxe2x88x92=(k/2)(VGS2xe2x88x92Vth)2xe2x80x83xe2x80x83(3) 
Subtracting equation (3) from equation (2) gives:                                                                         Iout                +                                  -                  Iout                                            -=                              xe2x80x83                            ⁢                                                (                                      k                    /                    2                                    )                                ⁢                                  xe2x80x83                                ⁢                                  (                                                            V                      GS1                                        +                                          V                      GS2                                        -                                          2                      ⁢                      Vth                                                        )                                                                                                                        xe2x80x83                            ⁢                              (                                                      V                    GS1                                    -                                      V                    GS2                                                  )                                                                                        =                              xe2x80x83                            ⁢                              k                ⁢                                  xe2x80x83                                ⁢                                  (                                      VB                    -                    Vth                                    )                                ⁢                                  xe2x80x83                                ⁢                Vin                                                                        (        4        )            
where VGS1, VGS2 are the gate-source voltages of the MOS transistors M1 and M2, respectively, Vin is the input signal (differential input voltage), and VB is the midpoint voltage of the input signal. Because the input signal is assumed to be a complete differential signal, the relationship of VGS1+VGS2=2VB=constant is used.
Since k(VBxe2x88x92Vth) is constant in equation (4), it is understood that the differential current of the output is completely proportional to the input voltage. That is, taking out the output in the form of the differential current enables the completely linear characteristic to be realized as the input/output characteristic, while assuring a wider linearity. Actually, as long as the input conditions are fulfilled, the linear range can be expanded to the extent that the transistors M1 and M2 are kept in the saturation region.
Another necessary condition for processing an analog signal with high accuracy is that the differential circuit has a high common mode rejection capability. In the circuit of FIG. 1, which provides differential operation, the common mode gain is obviously equal to the voltage gain of the single common-source MOS transistor and very high. In other words, the circuit has a low common mode rejection capability. Thus, when the input signal includes no in-phase components, there is no problem. When the input signal includes in-phase components, however, the components are amplified and appear at the output. Therefore, when the circuit shown in FIG. 1 is used as it is, its application is limited because its common mode rejection capability is low.
To overcome this disadvantage, a circuit system with a high common mode rejection capability has been proposed in Jpn. Pat. Appln. KOKAI Publication No. 8-32372 (or Japanese Pat. No. 2638492). The circuit described in the publication is shown in FIG. 2. A general approach of providing a circuit with a high common mode rejection capability is to construct the input stage using a differential circuit. In the conventional circuit of FIG. 2, the input stage is composed of two pairs of differential circuits: one pair includes MOS transistors M11 and M12 and the other pair includes MOS transistors M13 and M14. The coupled point of the sources of the transistors M11 and M12 is biased by a current source 10. The coupled point of the sources of the transistors M13 and M14 is biased by a current source 11.
With this configuration, an input signal voltage of V1 is normally distributed to the MOS transistors M11 and M12 and the MOS transistors M13 and M14 in the form of a variation in the gate-source voltage. Since the ratio of the distribution varies dynamically according to the input signal voltage V1, the linear output for the input cannot be drawn from the drain current of each pair. As a result, a linearizing approach as shown in the circuit of FIG. 1 cannot be applied.
In FIG. 2, to overcome this problem, the drain current of the MOS transistor M12 is returned by a current mirror circuit composed of MOS transistors M15 and M16 and another current mirror circuit composed of MOS transistors M18 and M17, and is added to the current source 10. In addition, the drain current of the MOS transistor M13 is returned by a current mirror circuit composed of MOS transistors M20 and M21 and another current mirror circuit composed of MOS transistors M23 and M22, and is added to the current source 11.
With this configuration, the drain current of the MOS transistor M12 including a variation in the signal is all supplied from the MOS transistor M17, with the result that the current flowing through the MOS transistor M11 becomes a constant current 10. Similarly, the drain current of the MOS transistor M13 including a variation in the signal is all supplied from the MOS transistor M22, with the result that the current flowing through the MOS transistor M14 becomes a constant current I0. Consequently, the gate-source voltage of the MOS transistor M11 depends only on the constant current I0 and becomes a constant voltage independent of the input signal voltage V1. The gate-source voltage of the MOS transistor M14 depends only on the constant current I0 and becomes a constant voltage independent of the input signal voltage V1.
Therefore, all the input signal voltage V1 is applied between the gate and source of the MOS transistor M12 and between the gate and source of the MOS transistor M13. The voltage applied between the gate and source of each of the MOS transistors M11 to M14 is expressed by the following equations:
M11: I0=(k/2)(VGS11xe2x88x92Vth)2xe2x80x83xe2x80x83(5) 
M12: Id12=(k/2)(VGS11xe2x88x92V1xe2x88x92Vth)2xe2x80x83xe2x80x83(6) 
M13: Id13=(k/2)(VGS14+V1xe2x88x92Vth)2xe2x80x83xe2x80x83(7) 
M14: I0=(k/2)(VGS14xe2x88x92Vth)2xe2x80x83xe2x80x83(8) 
where Id12 and Id13 are the drain currents of the MOS transistors M12 and M13.
From equation (5) and equation (8), VGS14=VGS11 holds. Taking this into account, subtracting equation (6) from equation (7) gives:
Id13xe2x88x92Id12=2k(VGS11xe2x88x92Vth)V1xe2x80x83xe2x80x83(9) 
Since VGS11=constant, equation (9) means that the differential current of the output is completely proportional to the input voltage, as equation (4) does. That is, drawing the output in the form of the differential current enables the completely linear characteristic to be realized as the input/output characteristic with a wide linearity.
Transistors M19 and M24 are used for output. The drains of the transistors M19 and M24 are connected to each other, thereby applying the input signal voltage V1 of opposite phase to a differential circuit composed of the transistors M11, M12, M15, M16, M17, and M18 and the current source 10 and to a differential circuit composed of the transistors M13, M14, M20, M21, M22, and M23 and the current source 11, and doing the sum of the output currents (the drain currents Id12 and Id13 of the MOS transistors M12 and M13) of the differential circuits, which produces an output current Isq.
In this way, the circuit of FIG. 2 has the two advantages of having a high common mode rejection ratio because the input stage is composed of differential circuits and of having a good linearity over a wide input voltage range, which has been difficult to realized using conventional CMOS circuits.
This circuit, however, has disadvantages in that it has two current mirror circuits on one side, that is, four current mirror circuits on both sides and that a poor accuracy of these current mirror circuits would degrade the linearity. Moreover, the current mirror circuits are liable to degrade the frequency characteristic, causing the problem: the effect of correcting the linearity decreases in the high-frequency, making distortion liable to occur. Other problems are that the size of the circuit increases and the drawn current dissipation becomes larger, depending on the addition of the current mirrors.
As described above, although the circuit of FIG. 2 can theoretically solve the problems the conventional CMOS differential amplifier has, it has many practical-use problems when being applied to practical circuits.
In integrated circuits, to filter an analog signal, it is common practice to use a filter circuit constructed by combining several integrators composed of transconductance circuits (hereinafter, referred to as gm circuits) and capacitors. To filter an analog signal with low noise and low distortion, each gm circuit has to have a wide input dynamic range and a good linearity. As described above, however, it has been generally difficult to realize an analog circuit with a good linearity using a conventional CMOS circuit configuration.
For example, consider a case where a general differential circuit as shown in FIG. 3 is used as a gm circuit constituting a filter circuit. The circuit is composed of a pair of MOS transistors M31 and M32 whose sources are connected to each other and a MOS transistor M33 (or a current source 2Ib) for biasing the MOS transistors M31, M32. The drain current Id31 of the MOS transistor M31 is returned by a current mirror circuit 12 and added to the drain current Id32 of the MOS transistor M32. Then, the difference current between the drain current Id31 and Id32 is used as an output current Iout. Using the output current Iout, a capacitor CA is charged or discharged for integral action.
Consider a case where a differential signal is inputted to the circuit. It is assumed that both transistors have the same size and shape and are operating in the saturation region (or the pinch-off region). For the sake of simplicity, the short channel effect is not taken into consideration. In the saturation region, the characteristic of the MOS transistor can be expressed by the above equation (1). The descriptive equations for the MOS transistors M31 and M32 are expressed by the following equations (10) and (11):
M31: Id31=(k/2)(VGS31xe2x88x92Vth)2xe2x80x83xe2x80x83(10) 
M32: Id32=(k/2)(VGS32xe2x88x92Vth)2xe2x80x83xe2x80x83(11) 
Here, the following equations hold:
VGS31xe2x88x92VGS32=Vinxe2x80x83xe2x80x83(12) 
Id31xe2x88x92Id32=Ioutxe2x80x83xe2x80x83(13) 
where VGS31 and VGS32 are the gate-source voltages of the MOS transistors M31 and M32, and Vin is the differential input voltage.
Solving these equations gives:
Iout=kVin(VGS31xe2x88x92Vthxe2x88x92Vin/2)xe2x80x83xe2x80x83(14) 
2Ib=k{(VGS31xe2x88x92Vth)2xe2x88x92Vin(VGS31xe2x88x92Vth)+Vin2/2}xe2x80x83xe2x80x83(15) 
Substituting VGS31 obtained by solving equation (15) gives the output current Iout for the input voltage Vin, which is expressed by a very complicated equation. The reason for this is that VGS31 and VGS32 vary with the value of Vin. The fact that the output current Iout is expressed by such a complicated equation means that the output has complex distortion components.
Consequently, even if a filter circuit is constructed using a differential circuit as shown in FIG. 3 as a gm circuit, distortion is liable to occur and therefore it is impossible to do filtering while keeping a high-quality.
As described above, although some of the conventional differential amplifiers (e.g., transconductance circuits) enable a wide linearity and a high common mode rejection ratio, they have disadvantages in that their linearity is liable to deteriorate, their linearity is poor in the high-frequency region, their circuit size is large, and the dissipation current is large. It is therefore desired that they should be improved.
Furthermore, when a conventional differential circuit is used as a gm circuit serving as a component element of a continuous-time filter circuit composed of CMOS elements, this causes the problems that distortion is liable to occur and it is impossible to do filtering, while maintaining the signal performance.
A first object of the present invention is to provide a multipurpose differential amplifier which has not only a wide linearity and a high common mode rejection ratio but also a good linearity, an excellent high-frequency characteristic, a small circuit size, and a small dissipation current.
A second object of the present invention is to provide a filter circuit which has a wide linearity, a good linearity, and an excellent high-frequency characteristic.
The first object of the present invention is accomplished by providing a differential amplifier comprising: a first current source one end of which is connected to a power supply or a ground; a first MOS transistor of a first conductivity type whose drain is connected to the other end of the first current source and whose gate is connected to a first input terminal; a second MOS transistor of the first conductivity type whose source is connected to a source of the first MOS transistor and whose gate is connected to a second input terminal; a third MOS transistor of the first conductivity type whose drain is connected to the sources of the first and second MOS transistors, whose source is connected to the ground or the power supply, and whose gate is coupled to the other end of the first current source; a second current source one end of which is connected to the power supply or the ground; a fourth MOS transistor of the first conductivity type whose drain is connected to the other end of the second current source and whose gate is connected to the second input terminal; a fifth MOS transistor of the first conductivity type whose source is connected to a source of the fourth MOS transistor and whose gate is connected to the first input terminal; and a sixth MOS transistor of the first conductivity type whose drain is connected to a sources of the fourth and fifth MOS transistors, whose source is connected to the ground or the power supply, and whose gate is coupled to the other end of the second current source, wherein a differential signal is inputted to the first and second input terminals and a differential output is obtained from drains of the second and fifth MOS transistors.
The first object is further accomplished by providing a differential amplifier comprising: a first current source one end of which is connected to a power supply or a ground; a first MOS transistor of a first conductivity type whose drain is connected to the other end of the first current source and whose gate is connected to a first input terminal; a second MOS transistor of the first conductivity type whose source is connected to a source of the first MOS transistor and whose gate is connected to a second input terminal; a third MOS transistor of the first conductivity type whose drain is connected to the sources of the first and second MOS transistors, whose source is connected to the ground or the power supply, and whose gate is coupled to the other end of the first current source; a second current source one end of which is connected to the power supply or the ground; a fourth MOS transistor of the first conductivity type whose drain is connected to the other end of the second current source and whose gate is connected to the first input terminal; a fifth MOS transistor of the first conductivity type whose source is connected to a source of the fourth MOS transistor and whose gate is connected to a third input terminal; and a sixth MOS transistor of the first conductivity type whose drain is connected to the sources of the fourth and fifth MOS transistors, whose source is connected to the ground or the power supply, and whose gate is coupled to the other end of the second current source, wherein a differential signal is inputted to the second and third input terminals, a voltage substantially equal to the DC voltage of the differential signal is inputted to the first input terminal, and a differential output is obtained from drains of the second and fifth MOS transistors.
The first object is still further accomplished by providing a differential amplifier comprising: a first current source one end of which is connected to a power supply or a ground; a first MOS transistor of a first conductivity type whose drain is connected to the other end of the first current source and whose gate is connected to a first input terminal; a second MOS transistor of the first conductivity type whose source is connected to a source of the first MOS transistor and whose gate is connected to a second input terminal; a third MOS transistor of the first conductivity type whose drain is connected to the sources of the first and second MOS transistors, whose source is connected to the ground or the power supply, and whose gate is coupled to the other end of the first current source; a second current source one end of which is connected to the power supply or the ground; a fourth MOS transistor of the first conductivity type whose drain is connected to the other end of the second current source and whose gate is connected to a third input terminal; a fifth MOS transistor of the first conductivity type whose source is connected to a source of the fourth MOS transistor and whose gate is connected to the second input terminal; and a sixth MOS transistor of the first conductivity type whose drain is connected to the sources of the fourth and fifth MOS transistors, whose source is connected to the ground or the power supply, and whose gate is coupled to the other end of the second current source, wherein a differential signal is inputted to the first and third input terminals, a voltage substantially equal to the DC voltage of the differential signal is inputted to the second input terminal, and a differential output is obtained from the drains of the second and fifth MOS transistors.
The first object is still further accomplished by providing a differential amplifier comprising: a first current source one end of which is connected to a power supply or a ground; a first MOS transistor of a first conductivity type whose drain is connected to the other end of the first current source and whose gate is connected to a first input terminal; a second MOS transistor of the first conductivity type whose source is connected to a source of the first MOS transistor and whose gate is connected to a second input terminal; a third MOS transistor of the first conductivity type whose drain is connected to the sources of the first and second MOS transistors, whose source is connected to the ground or the power supply, and whose gate is coupled to the other end of the first current source; a second current source one end of which is connected to the power supply or the ground; a fourth MOS transistor of the first conductivity type whose drain is connected to the other end of the second current source and whose gate is connected to a third input terminal; a fifth MOS transistor of the first conductivity type whose source is connected to a source of the fourth MOS transistor and whose gate is connected to the second input terminal; and a sixth MOS transistor of the first conductivity type whose drain is connected to the sources of the fourth and fifth MOS transistors, whose source is connected to the ground or the power supply, and whose gate is coupled to the other end of the second current source, wherein a differential signal is inputted to the first and third input terminals, a voltage substantially equal to the DC voltage of the differential signal is inputted to the second input terminal, and a differential output is obtained from drains of the second and fifth MOS transistors.
With these circuit configurations, the input signal is inputted as the voltage between the gates of a pair of MOS transistors, a differential pair. Since one MOS transistor of the differential pair is biased with a constant current, the gate-source voltage is constant. As a result, the input signal is applied only to the other MOS transistor. The latter MOS transistor operates in the same manner as a common-source transistor does. Its operating point, however, does not depend on the input signal voltage and is determined only by the current source.
Consequently, a differential amplifier of the present invention, which is constructed by combining two units of an amplifier that performs amplification independent of the DC voltage of the input signal and which carries out differential operation, produces the same effect as that of a differential amplifier composed of conventional common source transistor pairs. This realizes a circuit that has a good linearity over a wide input range. Moreover, the advantage that the operating point of each MOS transistor in two sets of differential pairs does not depend on the input signal voltage and is determined only by the current source is maintained, which achieves a high common mode rejection ratio.
Furthermore, the second object of the present invention is accomplished by providing a filter circuit comprising a unit integrator, the unit integrator including: first to fourth current sources one end of each of which is connected to a power supply or a ground; a first MOS transistor of a first conductivity type whose drain is connected to the other end of the first current source and whose gate is connected to a first input terminal; a second MOS transistor of the first conductivity type whose drain is connected to the other end of the second current source and a first output terminal, whose source is connected to a source of the first MOS transistor, and whose gate is connected to a second input terminal; a third MOS transistor of the first conductivity type whose drain is connected to the sources of the first and second MOS transistors, whose source is coupled to the ground or the power supply, and whose gate is coupled to the other end of the first current source; a fourth MOS transistor of the first conductivity type whose drain is connected to the other end of the third current source and whose gate is connected to the second input terminal; a fifth MOS transistor of the first conductivity type whose drain is connected to the other end of the fourth current source and a second output terminal, whose source is connected to a source of the fourth MOS transistor, and whose gate is connected to the first input terminal; a sixth MOS transistor of the first conductivity type whose drain is connected to the sources of the fourth and fifth MOS transistors, whose source is connected to the ground or the power supply, and whose gate is coupled to the other end of the third current source; and a capacitor connected to the first and second output terminals.
The second object of the present invention is further accomplished by providing a filter circuit comprising a unit integrator, the unit integrator including: first to fourth current sources one end of each of which is connected to a power supply or a ground; a first MOS transistor of a first conductivity type whose drain is connected to the other end of the first current source and whose gate is connected to a first input terminal; a second MOS transistor of the first conductivity type whose drain is connected to the other end of the second current source and a first output terminal, whose source is connected to a source of the first MOS transistor, and whose gate is connected to a second input terminal; a third MOS transistor of the first conductivity type whose drain is connected to the sources of the first and second MOS transistors, whose source is connected to the ground or the power supply, and whose gate is coupled to the other end of the first current source; a fourth MOS transistor of the first conductivity type whose drain is connected to the other end of the third current source and whose gate is connected to a third input terminal; a fifth MOS transistor of the first conductivity type whose drain is connected to the other end of the fourth current source and a second output terminal, whose source is connected to a source of the fourth MOS transistor, and whose gate is connected to a fourth input terminal; a sixth MOS transistor of the first conductivity type whose drain is connected to the sources of the fourth and fifth MOS transistors, whose source is connected to the ground or the power supply, and whose gate is coupled to the other end of the third current source; and a capacitor connected to the first and second output terminals, wherein a first differential signal is inputted to one of the set of the second and fourth input terminals and the set of first and third input terminals and a second differential signal is inputted to the other set or the input terminals of the other set are connected to each other for use as a DC input terminal.
The second object is still further accomplished by providing a filter circuit comprising a unit integrator, the unit integrator including: first and second current sources one end of each of which is connected to a power supply or a ground; a first MOS transistor of a first conductivity type whose drain is connected to the other end of the first current source and whose gate is connected to a first input terminal; a current mirror circuit connected to the power supply or the ground; a second MOS transistor of the second conductivity type whose drain is connected to an output terminal and an output node of the current mirror circuit, whose source is connected to a source of the first MOS transistor, and whose gate is connected to a second input terminal; a third MOS transistor of the first conductivity type whose drain is connected to the sources of the first and second MOS transistors, whose source is connected to the ground or the power supply, and whose gate is coupled to the other end of the first current source; a fourth MOS transistor of the first conductivity type whose drain is connected to the other end of the second current source and whose gate is connected to the second input terminal; a fifth MOS transistor of the first conductivity type whose drain is connected to an input node of the current mirror circuit, whose source is connected to a source of the fourth MOS transistor, and whose gate is connected to the first input terminal; and a sixth MOS transistor of the first conductivity type whose drain is connected to the sources of the fourth and fifth MOS transistors, whose source is connected to the ground or the power supply, and whose gate is coupled to the other end of the second current source.
Although these circuit configurations take the form of differential circuits, the current flowing through the first and fourth MOS transistors is only the current supplied from the constant current source and is always constant, regardless of the input, which keeps their gate-source voltage constant at all times. As a result, the input voltage is applied only to the second and fifth MOS transistors. That is, although the circuit takes the form of a differential configuration, the first and fourth MOS transistors only do the job of applying a bias voltage to the second and fifth MOS transistors, respectively, and what is related to the voltage-current conversion of the actual signal is only the second and fifth MOS transistors on one side. Consequently, the voltage-current conversion of the input signal in the filter circuit is basically performed by the single transistor, which makes the conversion equation very simple. Furthermore, combining two units of differential pairs enables the distortion components to be removed under the principle explained later, which realizes a circuit having a good linearity over a wide input range.
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.
FIG. 1 is a circuit diagram to help explain a conventional differential amplifier;
FIG. 2 is a circuit diagram to help explain a conventional improved differential amplifier;
FIG. 3 is a circuit diagram showing an example of the configuration of a conventional differential amplifier used as a transconductance circuit in a filter circuit;
FIGS. 4 to 6 are circuit diagrams to help explain differential amplifiers according to a first embodiment of the present invention;
FIG. 7 is a circuit diagram of a modification of the differential amplifier shown in FIG. 6;
FIG. 8 is a circuit diagram of another modification of the differential amplifier shown in FIG. 6;
FIG. 9 is a circuit diagram of still another modification of the differential amplifier shown in FIG. 6;
FIG. 10 is a circuit diagram of a modification of the differential amplifier shown in FIG. 9;
FIG. 11 is a characteristic diagram showing the input/output characteristic of the differential amplifier shown in FIG. 10;
FIG. 12 is a characteristic diagram for the common mode input showing the dependence of the differential amplifier of FIG. 10 on the input voltage;
FIG. 13 is a circuit diagram of a modification of the differential amplifier shown in FIG. 10;
FIG. 14 is a circuit diagram to help explain another differential amplifier according to the present invention;
FIGS. 15 to 17 are circuit diagrams showing the configuration of a differential amplifier used as a transconductance circuit in a filter circuit to help explain a second embodiment of the present invention;
FIG. 18 is a circuit diagram of a modification of the circuit shown in FIG. 17;
FIG. 19 is a circuit diagram of a modification of the level shift circuit in the circuit of FIG. 18;
FIG. 20 is a circuit diagram showing the configuration of a differential amplifier used as a transconductance circuit in a filter circuit to help explain a third embodiment of the present invention;
FIG. 21 is a circuit diagram of a concrete configuration of a secondary BPF (band-pass filter) using the differential amplifier of FIG. 19;
FIG. 22 is a characteristic diagram showing the frequency characteristic of the filter circuit shown in FIG. 21;
FIG. 23 is a circuit diagram of a concrete configuration of a secondary BPF (band-pass filter) shown in FIG. 21;
FIG. 24 is a circuit diagram showing the configuration of a differential amplifier used as a transconductance circuit in a filter circuit to help explain a fourth embodiment of the present invention;
FIG. 25 is a circuit diagram of a concrete configuration of a secondary BPF (band-pass filter) using the differential amplifier of FIG. 24; and
FIG. 26 is a characteristic diagram showing the frequency characteristic of the filter circuit shown in FIG. 25.